The disclosure relates generally to a circuit and method for providing a reference signal to a regulator.
A regulator in electronic devices is designed to automatically maintain a constant level of an output signal, e.g., a voltage or current signal, by a feed-forward design or a negative feedback control loop. FIG. 1 shows a typical linear voltage regulator 100. In this example, a feedback control loop, which is formed by an error amplifier 102 and a transistor (pass element) 104, with sufficient gain may regulate the feedback voltage Vfb toward a fixed or externally preset reference voltage Vref at the non-inverting node of the error amplifier 102. The error amplifier 102 drives the transistor 104 with more current if the voltage at its inverting node drops below the reference voltage signal Vref. Using a voltage divider 106, 108 allows choice of an arbitrary output voltage level Vout between levels of the reference voltage Vref and input voltage Vin. During the start-up phase of the voltage regulator 100, a fixed slew-rate reference signal generator 110 is typically employed for slowly ramping-up the reference voltage signal Vref in a controlled manner toward a preset voltage level Vset when transiting into the steady-state phase. In the start-up phase, the first switch 112 of the reference signal generator 110 is turned on while the second switch 114 is turned off such that the current source 116 continues charging the capacitor 118 by applying a constant charging current signal lc. The slew-rate of the reference voltage signal Vref at one end of the capacitor 118 is then fixed at a value determined by the charging current Ic and the capacitor 118. In the steady-state phase, the first switch 112 is turned off while the second switch 114 is turned on such that the reference voltage signal Vref is maintained at the preset voltage level Vset.
In an ideal situation, with control of the slew-rate of the reference voltage signal Vref within the control loop bandwidth of the voltage regulator 100, the feedback voltage Vfb, and eventually the output voltage Vout, will follow the reference voltage Vref and rise toward the preset voltage level Vset with minimal or no overshoot. However, in the event that the slew-rate of either the input voltage signal Vin or supply voltage (bias) signal Vdda of the voltage regulator 100 is slower than the slew-rate required for proper regulation of the output voltage Vout to follow the reference voltage signal Vref, as shown in FIGS. 2A and 2B, the output voltage Vout constrained by the input voltage signal Vin or the supply voltage signal Vdda may not be regulated by the reference voltage signal Vref and the feedback control loop of the voltage regulator 100 will become saturated. For example, in FIG. 2A, the output voltage Vout is not regulated to follow the reference voltage signal Vref due to the constraint imposed by the input voltage signal Vin. In FIG. 2B, the output voltage Vout is not regulated to follow the reference voltage signal Vref due to insufficient headroom (too low Vdda) for error amplifier 102 to regulate the output voltage Vout. The proper regulation of the output voltage Vout may require (1) the input voltage signal Vin is larger than the output voltage Vout(Vin>Vout) and (2) the supply voltage signal Vdda is larger than the output voltage Vout plus the headroom voltage of the error amplifier 102 (Vdda>Vout+Vheadroom). When the input voltage signal Vin in FIG. 2A or the supply voltage signal Vdda in FIG. 2B eventually exceeds the level required for proper regulation of the output voltage Vout toward the preset voltage level Vset, the feedback control loop of the voltage regulator 100 will try to regain regulation. However, during this process, an overshoot may occur when the output voltage signal Vout exceeds the preset voltage level Vset for a transient period, as shown in FIGS. 2A and 2B, which is undesirable for devices that are sensitive to overshooting, like processor. During this transient, the feedback control loop of the voltage regulator 100 exits from saturation state and attempts to enter into regulation state. It is understood that although a voltage regulator 100 is shown in FIG. 1, the same overshooting problem may also occur for a current regulator where an output current signal is regulated by a feedback control loop maintained by a reference voltage signal if the slew-rate of the reference voltage signal is faster than that of the input voltage signal or supply voltage signal of the current regulator in its start-up phase.
Known solutions to solve the overshooting problem include (1) designing the slew-rate of the reference signal to be slower than that of the input signal and (2) applying an external capacitor based on the known slew-rate of the input signal. For the former solution, it typically requires more silicon area to achieve a slower slew-rate for the reference signal and may encounter a practical limitation on the lowest slew-rate that can be implemented. As to the latter solution, it is costly as it uses an extra external capacitor and I/O pin. Further, if the slew-rate of the input signal is slower than its recommended value based on a chosen capacitor, an overshoot may still occur for the latter solution. Moreover, neither solution can be applied if the input signal of the regulator has a wide varying rise-time.
Accordingly, there exists a need for an improved circuit and method for providing a reference signal to a regulator.